(1) Field of the Invention
The present invention relates to a computer system, a compiler apparatus, and an operating system, and particularly to a computer system that has a cache memory as well as to a compiler apparatus and an operating system that are used in the computer system.
(2) Description of the Related Art
Recent years have seen a remarkable increase in the computing speed of processors, but the access speed to the main memory has not been increased much, when compared with processors. A widening gap between the processing speeds of processors and main memories has an adverse influence on the improvement in processor performance due to latency in accessing the main memory caused by reading/writing instructions or data.
With the aim of reducing latency in memory access, recent processors are equipped with a lower-capacity memory, known as cache memory, to which a relatively high-speed access can be made, in addition to the main memory. In a computer with such configuration, it is possible to store, on the cache memory, some of the instructions or data stored in the main memory. Accordingly, it becomes possible to reduce latency that occurs when the processor accesses the main memory and therefore to prevent processor performance from being affected by latency.
If there exists a target instruction or data on the cache memory when a processor accesses the main memory, the processor can read/write such target instruction or data with a shorter latency than in the case of making an access to the main memory. If a target instruction or data does not exist on the cache memory, on the other hand, the processor reads/writes such target instruction or data from and to the cache memory after transferring, to the cache memory, some of the instructions or data stored in the memory including the target instruction or data. It takes much time to transfer data from the main memory to the cache memory, but in the general program sequence, it is highly likely that the processor accesses nearby addresses for a certain period of time after making an access to a certain address on the main memory. Because of this fact, it becomes possible to reduce latency if the processor makes an access to the main memory after transferring instructions or data to the cache memory, compared with the case where it makes a direct access to the main memory.
However, when a target instruction or data does not exist on the cache memory, processor processing is required to be suspended while instructions or data are transferred from the main memory to the cache memory, as a result of which the performance of the processor is degraded. In order to prevent such performance degradation, a variety of methods of circumventing cache miss are proposed.
For example, there is disclosed a technique in which a prefetch instruction is inserted into a part of a source program at the time of compiling the source program, and necessary instructions or data are transferred from the main memory to the cache memory before such instructions are executed (See Japanese Laid-Open Patent application No. 11-212802 (FIG. 2) or Japanese Laid-Open Patent application No. 11-306028 (FIG. 1), for example).
However, in the above methods, a prefetch instruction inserted at compile time is executed without exception when a program is executed without taking into consideration a state of the cache memory. This causes a problem that, on a multitasking execution environment, instructions and data used by a program with a higher priority are flushed from the cache memory because of the reason that instructions and data used by a program with a lower priority have been prefetched, and therefore that cache hit rates are lowered.
Furthermore, even when instructions or data used by a program with a lower priority are prefetched, such instructions or data used by the program with a lower priority are flushed from the cache memory while a program with a higher priority is executed, which causes another problem that such prefetch is performed in vain.